Another market segment that is closely associated with EDA is semiconductor intellectual property, or semiconductor IP. This market segment provides pre-designed circuits of varying complexity that may be used as-is or adapted for a particular application. Semiconductor IP allows highly complex chips to be designed in far less time since a lot of existing design work can be reused. Due to the strong dependence of IP use and reuse on EDA tools, these markets are typically viewed as one.
Digital VLSI Chip Design with Cadence and Synopsys CAD Tools free download
Verification tools examine either the logical or physical representation of the chip to determine if the resultant design is connected correctly and will deliver the required performance. There are many processes that can be used here. Physical verification examines the interconnected geometries to ensure their placement obeys the manufacturing requirements of the fab. These requirements have become very complex and can include far more than 10,000 rules. Verification can also take the form of comparing the implemented circuit to the original description to ensure it faithfully reflects the required function. Layout vs. schematic, or LVS, is an example of this process. Functional verification of a chip can also use simulation technology to compare actual behavior to expected behavior. These approaches are limited by the completeness of the input stimulus provided. Another approach is to verify the behavior of the circuit algorithmically, without the need for input stimulus. This approach is called equivalence checking and is a part of a discipline known as formal verification.
Digital VLSI Chip Design with Cadence and Synopsys CAD ToolsBOOK DETAILPaperback: 600 pages Publisher: Pearson; 1 edition (March 7, 2009) Language: English ISBN-10: 0321547993 ISBN-13: 978-0321547996Product Dimensions: 7.3 x 1.4 x 9 inches Shipping Weight: 8 ounces (View shipping rates and policies) Customer Reviews: 3.8 out of 5 stars13customer ratingsBook DescriptionKEY BENEFIT: This hands-on book leads readers through the complete process of building a ready-to-fabricate CMOS integrated circuitusing popular commercial design software. KEY TOPICS: The VLSI CAD flow described in this book uses tools from two vendors: CadenceDesign Systems, Inc. and Synopsys Inc. Detailed tutorials include step-by-step instructions and screen shots of tool windows and dialogboxes. MARKET: A useful reference for chip designers. 2ff7e9595c
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